Chip design of the single interrupt source of high-efficient multiple serial interface
A summary
With the technical constant development of the one-chip computer, the application of the one-chip computer is more and more extensive, among them the one-chip computers of series 51 are occupying a market greatly all the time with the low co dominant of the price. However, the one-chip computer serial oral quantity is not usually large, for example 8051 one-chip computers have a serial port only, in-service use will often carry on serial oral expansion. It is to utilize a plurality of interrupt sources that the classic method expands a plurality of serial ports, but in the embedded system, it is undoubtedly a large amount of wasteful use of resources to spend a large number of interrupt sources expanding the serial port.
For utilize original resource go, expand serial port better, design, utilize single interrupt source go, expand a plurality of serial port originally, chip that is designed single interrupt source of a multiple serial interface. This chip can cooperate with the one-chip computer to read and write and convey the data, and can guarantee a plurality of serial ports are too interrupted to omit detection and service. The next step, also to designing carrying on a series of rigorous emulation and simulation result analysis. The result shows, this design has higher using value.
2 overall designs
2.1 chip designs
It is to integrate several pieces of tandem transceiver module on the chip together to originally design, in receiving, utilize an interrupt source to put forward the interrupt request to one-chip computer, the read/write operation of the recombination one-chip computer chooses to inquire, carries on corresponding operation while finding a certain transceiver has data; In sending, are chosen to send by the one-chip computer. The chip is divided into two storeys functionally, the lower floor includes the tandem transceiver. Cut off three pieces of module of control and management and address latch, the signal connected sum that the module of upper strata is responsible for the call, module of puocessing module controls the outward transport data or mark bit.
The module of top level: Finish each module signal connection of lower floor, handle the data well and mark conveying according to different addresses, choice scheduling problem of the transceiver.
Cut off the Administration Module: Store and manage the mark bit of each transceiver module, if some transceiver has interrupt requests that send out the interrupt signal to the one-chip computer regularly. Transceiver module: Finish the conversion, machine format receiving and sending of the data format, buffer the data received, can store the data of the 8 bytes slowly at most. The module of address register: Keep the address in the enable bit negative edge of address latch. This module has already been put into the module of top level.
2.2 The chip is connected with one-chip computer
The purpose of the chip design is for expanding the serial port of one-chip computer, seem essential that so how to unite the work with the one-chip computer.
Originally design the chip to connect with hardware of the one-chip computer simpler, among them, the data port d_inout runs side by side to link up with one piece machine p0 mouth, receive 8 low bit addresses that the one-chip computer sends out, ale links with address latch enabling signal pin of the one-chip computer, odd_check export pin for the intersection of add even check and result, connect, decide by user.
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Tags: one-chip computer, the chip, the counter, the register, the transceiver
